1. Field of the Invention
The present invention relates, in general, to a NAND flash memory cell string, and, more particularly, to a new NAND flash memory cell string, which improves the size reduction characteristics and performance of a MOS-based flash memory device and increase memory capacity.
2. Description of the Related Art
Recently, a demand for flash memory in electric home appliances and portable electronic devices has rapidly increased, and an increase in the capacity of flash memory has been continuously required. In the future, reduction in the size of a cell device to that of 20 nm is predicted.
The degree of integration of NAND flash memory needs to be continuously increased with the development of Information Technology (IT) technology. The degree of integration of NAND flash memory is greatly influenced by the degree of integration of a cell device. Recently, the length of the gate of a cell device has been reduced below 50 nm, and the capacity of memory has reached several tens of Giga bits. Because of this tendency, a Multi-Level Cell (MLC) having a U-shape floating-poly electrode (U-shape floating-poly cell for MLC NAND flash memory devices in the 13th Korean Conference on Semiconductors, p. 103, 2006), which realizes a high coupling effect and low crosstalk using existing floating gates, was published by the Samsung Electronics Co. Ltd. However, with the reduction in the size of cells, in order to form a U-shape floating-poly electrode, the pitch of the poly electrode in the direction of channel width increases to about 100 nm or more, thus causing problems. Further, with the reduction in the size of cells, a U-shape structure and an existing structure exhibit a serious short-channel effect at a gate length of about 45 nm or less. Further, demands for a multi-level cell have increased, but such a serious short-channel effect attributable to the size reduction of cell devices increases the distribution of threshold voltages at the time of implementing a multi-level cell, and thus great difficulty is expected. The degree of integration can be improved only when the length of a gate is continuously reduced in the future. For this requirement, an alternative plan must be considered. In order to improve the degree of integration of a device having an existing floating-poly electrode, various types of research have been conducted and various products have been developed. As examples of the results of such research, there are memory cells, each having a three-dimensional structure such as a Fin field effect transistor (FinFET) and a recessed channel device, and flash memory devices such as Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory and Nano-Floating Gate Memory (NFGM) using a nitride film or an insulating storage electrode. Such a device has become one plan for solving the problem of size reduction of flash memory having existing floating-poly electrodes. However, such an improved device also faces a problem in that device characteristics have greatly decreased due to a short-channel effect or in that a reduction in size is impossible in the case of a gate length corresponding to 40 nm or less.
In order to suppress a short-channel effect and reduce the distribution of threshold voltages, occurring when the gate length of a cell device is reduced to 40 nm or less, a SONOS cell device (or TaN—AlO—SiN-Oxide-Si: TANOS) having an asymmetric source/drain structure in a flat channel device (K. T. Park et al, A 64-cell NAND flash memory with asymmetric S/D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006) was published by the Samsung Electronics Co. Ltd. This shows a structure in which a source or drain region is present on one side and is not present on the other side around the gate of a cell device. Further, this structure denotes a structure in which an inversion layer is formed in the region having no source or drain using a fringing electric field generated from a control electrode, thus suppressing a short-channel effect. Compared to an existing SONOS cell device having a flat channel with source/drain regions, size reduction characteristics may be improved. However, since either one of the source and drain of the cell device is formed to overlap the control electrode, a short-channel effect is exhibited at a channel length of 40 nm or less, thus facing a limitation in the size reduction of a flat channel structure.
A flash device structure in which a channel is recessed and a conductive floating gate is used as a storage electrode so as to reduce a short-channel effect occurring in the existing flat channel structure (S.-P. Sim et al, Full 3-dimensional NOR flash cell with recessed channel and cylindrical floating gate—A scaling direction for 65 nm and beyond, in Technical Digest of Symposium on VLSI Technology, p. 22, 2006) was published by the Samsung Electronics Co. Ltd. In this case, with reduction in the size of the device, the width of a recessed region must be reduced, thus increasing the characteristic resistance of the device and the non-uniformity of the device.
The present inventor proposed a cell string composed of cell devices having no source/drain as in the case of the present invention in Korean Patent Appln. No 10-2006-0121143, entitled “High-Integration Flash Memory Cell String, Cell device, and Method of Manufacturing the Same.” The present invention shows a modification of this patent. The present invention is intended to improve ON-current characteristics in a read operation by forming a buried insulating layer.
In this way, the development of new high-integration/high-performance flash memory device, capable of suppressing a short-channel effect attributable to a reduction in size and the deterioration of performance which are problems of the above-described existing published devices, has been required.